SOC Limits Management Architect

What you'll do

• Define SoC limits management through hardware triggers, firmware policies, and software mitigations; standardize mitigation features across IP and hardware blocks.
• Drive sensing IP and trigger-mechanism evolution, and define real-time telemetry requirements and mitigation performance-impact profiles.
• Lead cross-functional technical decisions and oversee post-silicon validation against architectural intent.

What they ask for

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low-Power Design/Methodology.
• Experience across the product delivery cycle from architecture definition through post-silicon productization.
• Experience with low-power architectures and advanced power optimization techniques.

Nice to have

• MS or PhD in Electronics or Computer Engineering, or equivalent, focused on computer architecture and power/performance analysis.
• Experience with peak power management, power budgeting, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management, thermal management and AI.

Pay

$174,400.00 - $261,600.00 USD base salary

Tools

Power Telemetry, Estimators, Droop Detectors, Sensing IPs, Voltage, Current, Temperature, PDN

AI focus

AI is mentioned as a preferred area of experience; no specific AI work is described.