Qualcomm
Software Engineer — RISC-V Random Test Generator
$176K–$263K
Cupertino, California · On-site · Full-time · Posted Oct 2, 2026
- Experience
- The role description asks for 2–5 years in CPU design verification, ISS development, or hardware-software co-design. Minimum qualifications also specify 4+ years with a bachelor’s, 3+ with a master’s, or 2+ with a PhD.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Develop a Python-based RISC-V random test-generation framework and assembler library for CPU design verification, creating tests and instruction encodings to improve RTL coverage.
What you'll do
- Implement generation objects, test themes, and composable scenarios for RISC-V extensions and micro-architectural behaviors.
- Add assembler instruction forms and verify bit-level encodings against the RISC-V ISA specification.
- Support privileged-software sequences and collaborate with ISS/RTL verification engineers to triage failures and tune regressions and constraints.
What they ask for
- Solid Python 3 skills, including generator-based coroutines and object-oriented design.
- Working knowledge of RISC-V ISA details or similar knowledge of x86 or ARM.
- Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
- Bachelor’s degree in a related field and 4+ years of relevant experience, or master’s and 3+ years, or PhD and 2+ years.
Nice to have
- Exposure to random test-generation flows or ISS/RTL co-simulation.
- Compiler development, hypervisor and/or AIA/IMSIC architecture, or constraint-propagation library familiarity.
Pay
$175,600.00 - $263,400.00 (base salary)
Tools
Python 3, RISC-V, ELF, ISS, RTL, Sv39/Sv48, PMP, IMSIC
Model-written summary · the original posting is authoritative