Qualcomm
Sr. Staff Packaging Engineer- Process Package Integrity & Bumping
$192K–$288K
San Diego, California · On-site · Senior Staff · Full-time · Posted Sep 25, 2026
- Experience
- 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production; minimum qualifications also state 6+ years with a bachelor’s, 5+ with a master’s, or 4+ with a PhD.
- Education
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field; OR master's degree in those fields or related field; OR PhD in those fields or related field.
About the job
Leads wafer bumping and Far-BEOL process integration, qualification, and production readiness for advanced packaging across technology nodes, foundries, and assembly partners.
What you'll do
- Define bumping process flows, process windows, and controls; lead DOE-based optimization to improve yield, reliability, and cost.
- Lead bumping line bring-up, qualification, production release, and high-volume readiness with foundries and OSATs.
- Develop bumping solutions for flip-chip, RDL/fan-out, and 2.5D/3DIC packaging in collaboration with internal teams and suppliers.
What they ask for
- Bachelor’s degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of relevant work experience; OR master’s degree and 5+ years; OR PhD and 4+ years.
- Hands-on experience in silicon interconnect, bumping and/or RDL process, technology qualification, and production.
- Expertise in Far-BEOL bumping process integration, characterization, qualification, and manufacturing execution.
- Experience with supplier management, bumping house/OSAT operations, and process or production ramp.
Pay
$191,800.00 - $287,800.00 (USD, base salary)
Tools
Calibre, Virtuoso, CAD, SiP, GDS
Model-written summary · the original posting is authoritative