Qualcomm
Sr. Staff/Principal PCIE Subsystem Architect
$190K–$285K
Santa Clara, California +2 · On-site · Senior Staff · Full-time · Posted Sep 17, 2026
- Location
- Santa Clara, California
Austin, Texas
San Diego, California - Experience
- Bachelor’s: 10+ years; master’s: 8+ years; PhD: 6+ years of related work experience. Also requires 3+ years with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces. An earlier qualification section lists alternative ASIC experience thresholds: bachelor’s: 6+ years; master’s: 5+ years; PhD: 4+ years.
- Education
- Bachelor’s, master’s, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related field.
About the job
Defines and delivers high-performance PCIe subsystem architectures for next-generation datacenter AI products, from accelerator cards and servers to rack-scale deployments.
What you'll do
- Define subsystem architecture and drive requirements across accelerator, server, and rack-scale deployments.
- Address high-speed I/O architecture, including PCIe ordering, Gen6/Gen7 features, error recovery, virtualization, RAS, telemetry, and security.
- Coordinate technical requirements and alignment across engineering teams and stakeholders.
What they ask for
- Experience with PCIe, Ethernet, or other high-speed I/O interfaces in high-performance designs.
- Knowledge of PCIe ordering, DMA flows, PCIe Gen6/Gen7, error containment and recovery, I/O virtualization, and server-class RAS and security.
- Bachelor’s degree in a related field and 10+ years, master’s degree and 8+ years, or PhD and 6+ years of related work experience.
- 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.
Nice to have
- Familiarity with PCIe CEM, retimers, signal integrity, and system validation.
- Knowledge of UCIe, UALink/UAL, UEC, and PCIe security features such as IDE, DOE/SPDM, and TDISP.
Pay
$190,200.00 - $285,400.00 USD (pay range; salary/base pay).
Tools
PCIe, CXL, Universal Chiplet Interconnect Express (UCIe), Non-Volatile Memory Express (NVMe), Ethernet, ARM, SR-IOV, SIOV
AI focus
Architects high-performance I/O connectivity for next-generation AI datacenter products and accelerator subsystems.
Model-written summary · the original posting is authoritative