Qualcomm
Staff IC Packaging Engineer - Mechanical Simulation
$160K–$240K
San Diego, California · On-site · Staff · Full-time · Posted Oct 20, 2026
- Experience
- Minimum experience varies by degree: 4+ years with a bachelor's, 3+ years with a master's, or 2+ years with a PhD; preferred qualifications also specify 6+ years in IC package/interconnect FEA, 3+ years in ANSYS, and 4+ years in semiconductor and IC packaging.
- Education
- Bachelor's, master's, or PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or a related field.
About the job
Provides mechanical finite element simulation support for IC package designs, reliability prediction, and advanced packaging technologies.
What you'll do
- Develop and maintain FEA models, APDL macros, workflows, and methodologies for test correlation and material characterization.
- Perform warpage and stress analysis, solder joint reliability prediction, package assembly process simulation, and chip-package interaction analysis.
- Use advanced FEA techniques to predict failures and support package design, manufacturing, and reliability needs.
What they ask for
- Bachelor's degree in a related field plus 4+ years of related experience; or master's plus 3+ years; or PhD plus 2+ years.
- 6+ years of combined experience in FEA modeling and analysis for IC electronic packages and interconnects.
- 3+ years of experience in ANSYS (APDL/Workbench).
- 4+ years of direct experience in the semiconductor and IC microelectronic packaging industry.
Nice to have
- Research and publications in FEA predictive modeling, warpage, CPI, or solder lifetime prediction.
- Experience using internal AI tools to accelerate APDL coding and improve simulation workflows.
Pay
$160,200.00 - $240,200.00 USD base salary
Tools
ANSYS, APDL, Workbench, FEA
AI focus
Use internal AI tools to accelerate APDL coding and improve simulation workflows (preferred).
Model-written summary · the original posting is authoritative