Qualcomm
Staff SOC Physical Design Engineer
$152K–$210K
Austin, Texas · On-site · Staff · Full-time · Posted Sep 17, 2026
- Experience
- Three (3) years of experience in a related occupation.
- Education
- Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
About the job
Leads SoC physical-design flows and optimization, from floor planning through timing closure and physical verification, to support signoff and tapeout.
What you'll do
- Plan and perform floor planning, Clock Tree Synthesis, Place and Route, PDN, and timing analysis and closure.
- Run chip- and block-level physical verification, including LVS, DRC, design-for-manufacturing, and design-for-yield checks.
- Coordinate schedules and cross-functional engineering work to drive signoff closure for tapeout.
Pay
$152,360.00 - $210,000.00/year (base salary)
Tools
DDR, LVS, DRC
Model-written summary · the original posting is authoritative