Drimva

Qualcomm

System Performance Modeling Engineer

$122K–$183K

San Diego, California · On-site · Full-time · Posted Sep 17, 2026

Experience
Preferably 2–5 years of SoC modeling and/or software development; new graduates may be considered with strong internships and motivation. Also states degree-dependent ASIC experience: bachelor's plus 2+ years, master's plus 1+ year, or PhD.
Education
Degree in Microelectronics, Computer Science, or related field. Minimum qualifications also specify a bachelor's or master's degree in Science, Engineering, or related field, or a PhD.

About the job

Models and explores SoC platform architecture, especially NoC and memory systems, to assess performance and power trade-offs and inform future hardware designs.

What you'll do

  • Run NoC topology and system memory architecture exploration, analyzing data to inform next-generation SoC requirements.
  • Drive performance and power investigations across NoC, memory subsystem, system cache, and memory controllers.
  • Develop, maintain, and document tools and modeling frameworks for architecture exploration and validation.

What they ask for

  • Degree in Microelectronics, Computer Science, or a related field.
  • Understanding of computer architecture, memory hierarchy, and system/platform architecture.
  • Strong knowledge of Object-Oriented Programming (C++, Python).
  • Understanding of interconnect protocols such as AHB/AXI/ACE/ACE-Lite and NoC concepts and topologies.

Nice to have

  • Master's or PhD degree in a related field; strong mathematical background.
  • Knowledge of memory controller, LPDDR, and DDR protocols; experience with architecture-oriented performance and power investigations is a plus.

Pay

$121,800.00 - $182,600.00 USD base salary

Tools

C++, Python, AHB, AXI, ACE, ACE-Lite, LPDDR, DDR

AI focus

Support exploratory methodology projects involving machine learning and data science.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 4, 2026 (UTC)