Drimva

Qualcomm

VLSI Design Engineer for Server / Data Center Products

$146K–$218K

San Diego, California +2 · On-site · Full-time · Posted Sep 17, 2026

Location
San Diego, California
Santa Clara, CA
Austin, TX
Experience
4+ years with a bachelor’s degree, 3+ years with a master’s degree, or 2+ years with a PhD. Preferred qualifications also state 5+ years of relevant experience in ASIC design, scripting, and architecture.
Education
Bachelor’s degree in Science, Engineering, or related field; OR Master’s degree in Science, Engineering, or related field; OR PhD in Science, Engineering, or related field.

About the job

Design and develop RTL, architecture, verification, and integration for high-performance ASICs and SoCs serving server, data center, HPC, and AI applications.

What you'll do

  • Define and implement ASIC/SoC architecture and logic design, including large-scale integration and system simulation.
  • Execute design and verification strategies; resolve architecture, design, and verification problems.
  • Contribute to design reviews, process and automation improvements, and feedback on silicon learnings.

What they ask for

  • Bachelor’s degree in Science, Engineering, or related field and 4+ years of relevant work experience; OR Master’s degree and 3+ years; OR PhD and 2+ years.
  • Experience in ASIC design, verification, validation, integration, or related work.
  • Knowledge of server/data center IPs, protocols, and interfaces.
  • Experience designing arithmetic, computational, or machine-learning IPs.

Nice to have

  • Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering.
  • Experience in scripting and architecture; tool and process automation experience is an advantage.

Pay

$145,600.00 - $218,400.00 USD base salary

Tools

ASIC, FPGA, RTL, SoC

AI focus

Design work includes AI and machine-learning spaces, including arithmetic, computational, or machine-learning IPs.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)