River AI
Compiler Engineer, Hardware
$200K–$420K
Palo Alto, CA +1 · Full-time · Posted May 15, 2026
- Location
- Palo Alto, CA
Austin, Texas, United States - Experience
- 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- Visa sponsorship
- We sponsor visas; success is not guaranteed for every candidate or role.
About the job
Build a compiler stack that translates PyTorch models into optimized custom-ISA code for River AI’s high-performance silicon.
What you'll do
- Develop compiler passes, backends, and hardware-specific code generation, including scheduling and register allocation.
- Design tiling, fusion, and kernel integration strategies, and profile compiler performance gaps.
- Collaborate with AI, performance, RTL, and architecture teams on optimizations and custom ISA design.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 5+ years of practical industry experience working with advanced process nodes (7nm or below).
- Deep hands-on experience with MLIR or XLA for deep learning workloads, and expert understanding of PyTorch internals and external backends.
- Proficiency in modern C/C++ and advanced computer architecture knowledge for at least one chip style: SoCs, CPUs, GPUs, or AI accelerators.
Nice to have
- Hands-on experience in post-Silicon firmware and model update patches.
- Experience with custom dialects, lowering passes, and graph rewrites in an LLVM-based ecosystem; knowledge of static and runtime tradeoffs, including JITs and ABIs.
Pay
$200,000 - $420,000 USD annual salary (base salary).
Tools
PyTorch, MLIR, LLVM, Triton, CUDA, XLA, C/C++
AI focus
Develop compiler infrastructure that maps deep learning models to custom silicon for high-performance inference.
Model-written summary · the original posting is authoritative