River AI
Design Verification Engineer, Hardware
$200K–$420K
Palo Alto, CA +2 · Full-time · Posted May 15, 2026
- Location
- Palo Alto, CA
Austin, TX
Austin, Texas, United States - Experience
- 5+ years industry experience.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
- Visa sponsorship
- River AI sponsors visas; it cannot guarantee success for every candidate or role.
About the job
Verifies the functional correctness of custom silicon by developing and running simulation, formal, and emulation-based verification environments.
What you'll do
- Create verification plans and reusable UVM test benches; develop constrained-random tests and coverage models.
- Apply formal verification and emulation, debug failures with RTL designers, and analyze coverage.
- Build and maintain regression flows and verification productivity tools.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, and 5+ years industry experience.
- Hands-on experience building UVM-based environments and expert command of SystemVerilog verification.
- Strong understanding of computer architecture, including pipelines, cache coherency, memory consistency, and high-speed interconnects.
- Track record verifying high-performance silicon such as a CPU, GPU, AI accelerator, or complex SoC.
Nice to have
- Proficiency with SVA and formal tools such as Jasper or VC Formal; understanding of emulation and prototyping solutions.
- Post-silicon bringup, testing, and debug experience; workflow, CI/CD, regression, or EDA infrastructure experience.
Pay
$200,000 - $420,000 USD (base salary)
Tools
SystemVerilog, UVM, SVA, Jasper, VC Formal, ZeBu/HAPS, Palladium/Protium, Python
AI focus
Verifies custom silicon for personal hardware and local inference.
Model-written summary · the original posting is authoritative