River AI
Physical Design Engineer, Hardware
$200K–$420K
Palo Alto, CA +2 · Full-time · Posted May 15, 2026
- Location
- Palo Alto, CA
Austin, TX
Austin, Texas, United States - Experience
- 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- Visa sponsorship
- Visa sponsorship is available.
About the job
Own the physical implementation of a custom AI accelerator, from synthesis through tape-out, optimizing performance, power, and area and achieving design sign-off.
What you'll do
- Run synthesis, placement, clock tree synthesis, and routing; optimize PPA, timing, and power delivery.
- Resolve timing, signal integrity, electromigration, IR-drop, and physical verification issues.
- Partner with RTL designers and develop AI-driven EDA workflows to accelerate design closure.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Hands-on proficiency with physical design, timing, and sign-off tools; experience with logic synthesis, compiled memory macros, and multi-voltage design using UPF/CPF.
- Strong debugging skills and ability to collaborate with RTL and architecture teams.
Nice to have
- Delivered high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple production tape-outs; experience with highly parallel compute layouts or HBM interfaces.
- Experience scripting or extending EDA tools with Tcl, Python, or specialized ML APIs.
Pay
$200,000 - $420,000 USD annual base salary
Tools
Innovus, Fusion Compiler, PrimeTime, RedHawk, UPF/CPF, Tcl, Python
AI focus
Develop and integrate AI-driven EDA tools and workflows to accelerate physical implementation and optimize design closure for a custom AI accelerator.
Model-written summary · the original posting is authoritative