River AI
RTL Design Engineer, Hardware
$200K–$420K
Palo Alto, CA +1 · Full-time · Posted May 15, 2026
- Location
- Palo Alto, CA
Austin, Texas, United States - Experience
- 5+ years practical industry experience working with advanced process nodes (7nm or below).
- Education
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- Visa sponsorship
- Visa sponsorship is available; success is not guaranteed for every candidate or role.
About the job
Architects and implements high-performance custom silicon for AI accelerators and related SoC components, from microarchitecture and RTL through physical-design and performance integration.
What you'll do
- Define architectural specifications and detailed microarchitectures for AI hardware subsystems.
- Develop System Verilog RTL and collaborate with backend teams on synthesis, floorplanning, power analysis, and timing closure.
- Work with compiler, performance-modeling, and software teams to identify bottlenecks across the chip and system.
What they ask for
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- 5+ years of practical industry experience with advanced process nodes (7nm or below).
- Hands-on proficiency with industry-standard RTL, synthesis, physical design, and timing tools; expert computer-architecture knowledge of at least one chip style.
- Track record delivering functional, performant silicon, including ECOs and reliable silicon at scale.
Nice to have
- Post-silicon bug fixing, firmware patching, and GPIO/I2C/SPI/UART debugging.
- C/C++/python and ISA assembly; high-speed IO, memory-controller, or NoC experience.
Pay
$200,000 - $420,000 USD annual base salary
Tools
System Verilog, VCS/Verdi, Fusion Compiler, PrimeTime, C/C++/python, PCIe, UCIe, HBM/DDR
AI focus
Designs custom silicon for AI accelerators and AI hardware subsystems.
Model-written summary · the original posting is authoritative