RosaicLabs
AI Accelerator Design Verification Engineer - Intern
Santa Clara, CA +1 · On-site · Internship · Posted Oct 5, 2026
- Location
- Santa Clara, CA
Austin, TX - Education
- Working toward a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
About the job
Verifies accelerator blocks by developing testbenches, models, and coverage, then debugging failures with RTL designers.
What you'll do
- Develop verification plans and write and debug SystemVerilog/UVM testbenches, checkers, and stimulus.
- Build tests, scoreboards, and reference models; close functional and code coverage.
- Triage failures with RTL designers and document the verification environment and results.
What they ask for
- Working toward a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Recently completed coursework in digital design and verification covering at least one listed topic: computer microarchitecture, digital logic and RTL design, or constrained-random and coverage-driven verification.
- Hands-on SystemVerilog experience, including testbench development, assertions, and functional coverage.
- Understanding of the end-to-end ASIC design flow and general VLSI concepts; scripting experience in Python, Perl, or Tcl.
Nice to have
- UVM testbench experience.
- C/C++ experience.
Pay
USD 30–55 per-hour-wage
Tools
SystemVerilog, UVM, Python, Perl, Tcl, C/C++, DMA
AI focus
Verification of an AI accelerator design.
Model-written summary · the original posting is authoritative