RosaicLabs
CPU Design Verification Engineer - Intern
Santa Clara, CA +1 · On-site · Internship · Posted Oct 5, 2026
- Location
- Santa Clara, CA
Austin, TX - Education
- Working toward a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Verifies CPU cores and cache hierarchies by developing testbenches, tests, and coverage-driven verification environments.
What you'll do
- Develop verification plans and SystemVerilog/UVM testbenches, checkers, and stimulus.
- Build tests, scoreboards, and reference models, and close functional and code coverage.
- Triage failures with RTL designers and participate in reviews and documentation.
What they ask for
- Working toward a BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Recently completed coursework in digital design and verification covering at least one listed topic.
- Hands-on SystemVerilog experience, including testbench development, assertions, and functional coverage.
- Understanding of the end-to-end ASIC design flow and general VLSI concepts; scripting experience in Python, Perl, or Tcl.
Nice to have
- UVM experience.
- C/C++ experience.
Pay
USD 30–55 per-hour-wage
Tools
SystemVerilog, UVM, Python, Perl, Tcl, C/C++
Model-written summary · the original posting is authoritative