RosaicLabs
CPU RTL Microarchitecture/Design Engineer - Full Time
$125K–$250K
Santa Clara, CA +1 · Hybrid · Full-time · Posted Sep 29, 2026
- Location
- Santa Clara, CA
Austin, TX - Education
- Bachelor's or Master's degree (or near-term graduation) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Designs and optimizes CPU functional blocks in RTL, collaborating with verification and physical design teams to meet functional, performance, timing, area, and power goals.
What you'll do
- Design, debug, and optimize CPU RTL based on microarchitecture specifications.
- Analyze performance, timing, area, and power tradeoffs; collaborate on improvements and design goals.
- Work with verification engineers on test plans and functional coverage, and participate in design reviews and documentation.
What they ask for
- Bachelor's or Master's degree (or near-term graduation) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Strong foundation in computer architecture and digital design, including at least two listed CPU architecture areas.
- Working knowledge of a modern ISA.
- Hands-on Verilog/SystemVerilog experience, including RTL simulation and testbench-based debugging; familiarity with ASIC design flow and scripting.
Pay
USD 125,000–250,000 per-year-salary (base salary)
Tools
SystemVerilog, Verilog, Python, Perl, Tcl, C/C++
Model-written summary · the original posting is authoritative