SambaNova
Design Verification Engineer
$120K–$200K
San Jose, California, United States · Full-time · Posted Aug 18, 2026
- Experience
- 5+ years relevant industry experience
- Education
- B.S. in Computer Science, Computer Engineering, or related field
About the job
Develops and drives verification of chip-level control and initialization features for SambaNova’s RDU, from verification planning through debugging and closure.
What you'll do
- Create verification plans and SystemVerilog/UVM environments, tests, checkers, assertions, and functional coverage.
- Verify sequencing, dependencies, state transitions, clocking, and recovery across chip subsystems using directed and constrained-random tests.
- Debug simulations and regressions, analyze coverage, and coordinate with design and verification teams to resolve issues and reach closure.
What they ask for
- B.S. in Computer Science, Computer Engineering, or a related field.
- Strong understanding of digital design, SoC architecture, and verification methodologies.
- Strong proficiency in SystemVerilog and UVM; experience with constrained-random verification, functional coverage, and assertion-based verification.
- Proficiency in scripting languages such as Python, Perl, TCL, and shell scripting.
Nice to have
- Familiarity with CDC/RDC concepts and verification methodologies.
- Fluency in Claude / AI tools for verification development and debug.
Pay
$120,000 — $200,000 USD (base salary)
Tools
SystemVerilog, UVM, Python, Perl, TCL, shell scripting, Claude
AI focus
Use Claude / AI tools for verification development and debug.
Model-written summary · the original posting is authoritative