SambaNova
Design Verification Engineer, New Grad
$120K–$150K
San Jose, California, United States +1 · Entry level · Full-time · Posted Oct 27, 2026
- Location
- San Jose, California, United States
Austin, Texas, United States - Education
- B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field; M.S. preferred.
About the job
Verifies RDU chip-level control and initialization features by developing SystemVerilog and UVM tests, running regressions, and debugging issues before tape-out.
What you'll do
- Write verification plans and build testbench components, including sequences, checkers, assertions, and functional coverage.
- Develop directed and constrained-random tests; analyze coverage and close gaps.
- Run regressions and debug failures with RTL designers.
What they ask for
- B.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or project experience in digital design and computer architecture.
- Experience with SystemVerilog or Verilog, UVM, and scripting in Python, Perl, TCL, or shell.
- Familiarity with constrained-random verification, functional coverage, assertions, and clock domain crossing concepts.
Nice to have
- M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Experience using AI tools such as Claude for verification development and debug; internship experience in design verification.
Pay
$120,000 — $150,000 USD base salary
Tools
SystemVerilog, UVM, Verilog, Python, Perl, TCL, shell, Claude
AI focus
Preferred use of AI tools such as Claude for verification development and debug.
Model-written summary · the original posting is authoritative