Director of ASIC Design Verification

What you'll do

• Own verification architecture, methodology, quality, coverage closure, schedule, and tape-out readiness.
• Lead and develop an experienced DV team; direct emulation and FPGA prototyping and oversee verification tooling and vendor relationships.
• Partner across architecture, design, software, and systems teams on requirements, workload validation, and first-silicon debug.

What they ask for

• BS in EE, CS, or CE, with 12+ years (or equivalent) of industry experience in ASIC design verification.
• 5+ years managing design verification engineers, including hiring and performance management; experience leading senior and principal-level engineers.
• Full-cycle DV through tape-out and production silicon on at least one complex ASIC or large subsystem; experience with silicon bring-up and lab debug.
• Deep hands-on expertise in SystemVerilog, SVA, Python, and UVM, OVM, or VMM; working knowledge of machine learning SoCs or microprocessors and modern computer architecture.

Nice to have

• MS or PhD in EECS with 15+ years of experience in ASIC design verification.
• Experience with large-scale chips, post-silicon validation, performance verification, PCIe or Ethernet, memory subsystems, advanced TSMC nodes, chiplets, emulation/FPGA platforms, distributed teams, or AI tools applied to verification.

Pay

$270,000 — $340,000 USD base salary

Tools

SystemVerilog, SVA, Python, UVM, OVM, VMM, PCIe, Ethernet

AI focus

Land AI-assisted verification workflows; preferred experience applying Claude or other AI tools to verification and flow development.