Principal DFT Engineer

What you'll do

• Define and implement block- and SoC-level DFT architecture; develop ATPG flows and automation.
• Develop JTAG, IEEE 1500, and IEEE 1687/IJTAG infrastructure and generate ATPG and MBIST patterns for ATE.
• Support DFT timing closure, silicon diagnosis, failure localization, yield analysis, and manufacturing test optimization.

What they ask for

• B.S. in computer science, computer engineering, or related field.
• Deep understanding of scan insertion, scan compression, ATPG, MBIST, JTAG, and hierarchical DFT.
• Strong understanding of advanced ATPG, silicon diagnosis, and failure localization methodologies.
• Experience with STA constraints and analysis for DFT modes and SDF simulations; working knowledge of Verilog/System-Verilog simulators and waveform debugging.

Nice to have

• Siemens Tessent tool flow or equivalent industry-standard DFT tools; experience with ATE pattern deployment and silicon bring-up.
• Experience with multi-die/chiplet DFT, known-good-die test, die-to-die interface testing, or large compute, AI accelerator, or HPC SoCs.

Pay

$180,000 — $255,000 USD (base pay range)

Tools

Siemens Tessent, ATPG, MBIST, JTAG, IEEE 1500, IEEE 1687/IJTAG, Verilog/System-Verilog, SDF

AI focus

Develops and tests RDU chips for machine learning and artificial intelligence; the posting does not specify AI software or model development work.