SambaNova
Principal RTL Design Engineer
$180K–$255K
Austin, Texas, United States +3 · Principal · Full-time · Posted Aug 19, 2026
- Location
- Austin, Texas, United States
San Jose, California, United States
Austin, Texas, United States
San Jose, California, United States - Experience
- 7+ years of industry experience in ASIC RTL design.
- Education
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
About the job
Owns microarchitecture and RTL design for a major RDU block or subsystem, guiding it from specification through quality closure and ASIC tape-out while meeting PPA and frequency targets.
What you'll do
- Design, integrate, and debug synthesizable SystemVerilog RTL through chip implementation and production.
- Drive PPA, timing closure, and design quality, including synthesis, STA, lint, CDC, LEC, and assertions.
- Partner with verification, architecture, and software teams; lead design reviews, mentor engineers, and advance AI and EDA methodologies.
What they ask for
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
- Mastery of synthesizable SystemVerilog and SVA for high-performance ASICs, with high-frequency datapath and microarchitecture design experience.
- Owned a complex block or subsystem from specification through tape-out on at least one production ASIC; experience converging PPA under physical constraints.
- Hands-on synthesis, static timing analysis, lint, CDC, and LEC experience; Python scripting; demonstrated technical leadership.
Nice to have
- M.S. or Ph.D. in a relevant field; depth in compute/dataflow, interconnect, or memory subsystems.
- Experience with AXI, PCIe, Ethernet, HBM or DDR; AI/ML acceleration, formal property checking, advanced TSMC nodes, chiplets, or AI tools applied to RTL.
Pay
$180,000 — $255,000 USD base salary
Tools
SystemVerilog, SVA, Python, AXI, PCIe, Ethernet, HBM, DDR
AI focus
Drive AI, automation, and new EDA tool methodologies into the design flow; preferred experience applying AI tools to RTL design and flow development.
Model-written summary · the original posting is authoritative