Senior Hardware Design Engineer

What you'll do

• Author microarchitecture specifications and code, integrate, and debug SystemVerilog RTL for assigned blocks.
• Meet PPA targets and collaborate with verification and physical design teams on functionality, timing, and area.
• Run design checks and support post-silicon bring-up and debug; contribute to design-flow improvements, including AI and EDA automation.

What they ask for

• Master’s degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor’s degree with 5–7 years.
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs; foundation in computer architecture and digital logic design.
• Experience with PPA tradeoffs, synthesis and STA, lint, CDC, LEC, and SVA.
• Working knowledge of industry-standard interconnects and protocols; Python and Linux shell scripting; ability to work onsite in San Jose, CA or Austin, TX.

Nice to have

• Exposure to a full ASIC development cycle through tapeout and production silicon; interest in or knowledge of AI workload acceleration.
• Low-power design experience at advanced process nodes or exposure to emulation or FPGA prototyping.

Pay

$120,000 — $200,000 USD (base salary)

Tools

SystemVerilog, AXI, PCIe, Ethernet, HBM/DDR, Python, Linux shell, Git

AI focus

Contributes to design-flow improvements, including AI and automation in EDA tool methodologies; works on hardware for AI workload acceleration.