SambaNova
Senior RTL Design Engineer
$120K–$200K
Austin, Texas, United States +3 · Senior · Full-time · Posted Aug 20, 2026
- Location
- Austin, Texas, United States
San Jose, California, United States
Austin, Texas, United States
San Jose, California, United States - Experience
- 5+ years of experience in ASIC RTL design.
- Education
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science; M.S. or Ph.D. preferred.
About the job
Designs and implements blocks for SambaNova’s RDU AI accelerator ASICs, carrying them from microarchitecture and RTL through tape-out and silicon bring-up.
What you'll do
- Contribute to block-level microarchitecture specifications and write and debug RTL.
- Make power, performance, and area trade-offs; take blocks through implementation and tape-out.
- Collaborate with architecture, verification, and physical design teams, including during silicon bring-up.
What they ask for
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science.
- 5+ years of experience in ASIC RTL design.
- Strong SystemVerilog RTL skills and a foundation in computer architecture and digital logic design.
- Experience with PPA trade-offs, industry-standard interconnects and protocols, synthesis and static timing analysis, lint/CDC/LEC tools, SystemVerilog Assertions, performance analysis, Git, Python, and Linux shell.
Nice to have
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science.
- Exposure to a full ASIC development cycle, AI workload acceleration, low-power design, or emulation/FPGA prototyping.
Pay
$120,000 — $200,000 USD (base salary)
Tools
SystemVerilog, AXI, PCIe, Ethernet, HBM, DDR, Git, Python
AI focus
Designs RDU AI accelerator ASICs; preferred interest in or knowledge of AI workload acceleration techniques.
Model-written summary · the original posting is authoritative