Intern, RTL Power Macromodeling Engineer

What you'll do

• Build and validate power models for AI-memory components using analytical models, lookup tables, FSMs, neural networks, or hybrids.
• Extract power features from RTL, SystemC, and C simulations, and calibrate models using synthesis, circuit references, and measured data.
• Compare models against RTL, gate-level power analysis, and silicon; deliver validated models and regression checks into the simulation flow.

What they ask for

• MS or PhD in Electrical and Computer Engineering, Computer Science, or a related field.
• At least one academic quarter or semester remaining.
• RTL design and analysis experience with Verilog, SystemVerilog, or SystemC, plus solid C++ or Python.
• Understanding of dynamic and leakage power in CMOS and interconnect, and ability to abstract circuit behavior into compact models.

Nice to have

• Experience with PrimeTime PX, StarRC, VCS, PowerArtist, McPAT, CACTI, Wattch, S-parameters, SPICE, UCIe, high-speed I/O, or 2.5D packaging.

Pay

$28 — $68 USD hourly base pay rate

Tools

Verilog, SystemVerilog, SystemC, C++, Python, PrimeTime PX, StarRC, VCS

AI focus

Developing power macromodels for AI-memory components, including models using neural networks, and supporting trace-driven power and thermal simulation.