Samsung
Principal Engineer, SOC Design
$219K–$351K
San Jose, California, United States · Principal · Full-time · Posted Sep 3, 2026
- Experience
- 20+ years with a bachelor's degree, 18+ years with a master's degree, or 15+ years with a PhD; the posting describes these qualifications as preferred.
- Education
- Bachelor's, master's, or PhD in Electrical, Computer Science, or a related field.
About the job
Designs and integrates memory and storage SoCs, from architecture and RTL implementation through verification support, physical design coordination, and silicon bring-up.
What you'll do
- Define subsystem or chip-level architecture and microarchitecture; implement logic and RTL.
- Integrate third-party IP and subsystems, and perform quality checks including assertion, lint, CDC, and STA.
- Coordinate with architects, verification engineers, and physical designers on SoC design, timing, synthesis, DFT, and analysis.
What they ask for
- Hands-on knowledge of ASIC design flow from design to tape out.
- Experience in ATE vector generation, testing, and silicon bring-up.
- Experience with commercial IP such as UCIe, CPU, Ethernet, and DDR interfaces.
- Experience in SoC-level synthesis, timing analysis, lint, and CDC checks.
Nice to have
- Good knowledge of AMBA bus fabric and ARM cores.
- Experience interfacing with third-party service companies for DFT/PI/PD.
Pay
$219,000 — $351,000 USD (base salary)
Tools
ASIC, RTL, ARM, DDR, UCIe, Ethernet, AMBA, DFT
AI focus
Develops prototype and production memory and storage controllers for computing architectures supporting emerging machine learning applications, data analytics, and edge computing. AI is also used as a support tool in recruitment.
Model-written summary · the original posting is authoritative