Samsung
Senior Engineer, Physical Design AI/ML
$138K–$206K
San Jose, California, United States · Senior · Full-time · Posted Aug 31, 2026
- Experience
- Industry experience is preferred; no number of years stated.
- Education
- PhD preferred.
About the job
Researches and evaluates advanced logic technology options and applies AI/ML to improve chip design, simulation, and implementation for sub-2nm process nodes.
What you'll do
- Develop machine learning and generative models to optimize chip layouts for performance, power, and area (PPA).
- Automate design implementation, verification, and exploratory PDK generation and quality assurance.
- Analyze cross-domain data, build internal benchmarks, and share technology assessments with R&D teams.
What they ask for
- Skills in RTL synthesis, place and route, and timing analysis, plus understanding of clock and power delivery networks.
- Hands-on machine learning or deep learning project experience in scientific or engineering applications.
- Strong Python and/or C++ skills, including machine learning packages such as PyTorch and Tensorflow.
- Experience with Bayesian optimization and/or active learning frameworks; expertise with agentic AI frameworks (LangGraph, CrewAI, ADK).
Nice to have
- Experience optimizing DTCO knobs in advanced logic nodes (2nm or beyond).
- Familiarity with state-of-the-art AI workloads, private compute clusters for LLMs, EDA tools, or generative AI for chip design/optimization.
Pay
$138,000 — $206,000 USD base salary
Tools
Python, C++, PyTorch, Tensorflow, LangGraph, CrewAI, ADK
AI focus
Applies machine learning and generative models to chip layout optimization, PPA prediction, design-space exploration, data correlation, and automation of design and verification workflows.
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