Samsung
Senior Engineer, PLL Design
$138K–$206K
San Jose, California, United States · Senior · Full-time · Posted Oct 5, 2026
- Experience
- Master's with 2+ years of experience or PhD with 0 years of experience.
- Education
- Master's or PhD in a related field.
About the job
Designs and develops high-performance PLL and clock-generation circuits for RF transceivers, SerDes, and high-speed I/O in advanced CMOS technologies.
What you'll do
- Design PLLs, clock-generation circuits, and critical PLL building blocks; perform system modeling, noise analysis, and jitter budgeting.
- Verify designs through transistor-level simulation, Monte Carlo analysis, and silicon correlation; collaborate across teams to meet performance, power, and area targets.
- Support silicon prototype bring-up, characterization, and lab debug.
What they ask for
- Master's with 2+ years of experience, or PhD with 0 years of experience, in a related field.
- Hands-on PLL design experience in deep-submicron CMOS (5nm-28nm), including at least one specified PLL topology.
- Understanding of PLL theory, layout-sensitive design, and lab characterization; experience with RTL design for PLL-related digital calibration circuits.
- Proficiency with IC design CAD tools and Matlab/Simulink; familiarity with Verilog/SystemVerilog for mixed-signal simulation.
Pay
$138,000 — $206,000 USD (base salary)
Tools
Matlab/Simulink, Spectre, SpectreRF, AMS simulator, Verilog, SystemVerilog
AI focus
The role does not involve AI development. The posting states that AI tools support recruitment, with human teams making hiring decisions.
Model-written summary · the original posting is authoritative