Samsung
Senior HSIO Digital Design Engineer
$138K–$206K
San Jose, California, United States · Senior · Full-time · Posted Jul 31, 2026
- Experience
- BS in Electrical Engineering with 5+ years; MS in Electrical Engineering with 3+ years; or PhD in Electrical Engineering. The posting also describes ideal candidates as having 3+ years of industry experience.
- Education
- BS, MS, or PhD in Electrical Engineering.
About the job
Designs digital components for next-generation high-speed I/O interfaces used in Samsung’s AI platforms, collaborating with system and analog teams.
What you'll do
- Develop high-speed I/O PHY IP for die-to-die or similar technologies.
- Work across the digital design flow and coordinate with system and analog teams.
- Apply knowledge of serial interconnect protocols, analog/mixed-signal design impacts, and signal and power integrity.
What they ask for
- Hands-on experience in High-Speed I/O PHY IP development.
- Strong understanding of high-speed serial interconnect protocols and design trade-offs.
- Understanding of how analog and mixed-signal design and verification affect digital-on-top development flows.
- Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
Nice to have
- Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link.
- Familiarity with HSIO PHY layer protocols and architectures.
Pay
$138,000 — $206,000 USD base salary
Tools
AXI, CHI, CXS.B, CXL, PCIE, UA-Link
AI focus
The role designs HSIO for Samsung’s AI production platforms. The posting also states that AI tools support recruitment, not hiring decisions.
Model-written summary · the original posting is authoritative