Samsung
Senior Physical Design Engineer
$138K–$206K
San Jose, California, United States · Senior · Full-time · Posted Aug 19, 2026
- Experience
- Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience; also asks for 5+ years of physical design implementation experience.
- Education
- Bachelor’s, Master’s, or PhD's.
About the job
Own physical implementation and signoff of memory-centric computing IP and SoC designs, optimizing performance, power, and area for AI/ML workloads.
What you'll do
- Implement designs from RTL netlist to GDSII, including synthesis, floorplanning, placement, clock tree synthesis, and routing.
- Drive PPA convergence, timing closure, physical verification, and signoff across blocks and full-chip designs.
- Develop and automate implementation flows using Tcl/Python scripting and agentic AI tools and frameworks.
What they ask for
- Strong background in digital physical design and VLSI implementation.
- Experience with physical design implementation for complex ASIC/SoC designs, including synthesis, floorplanning, place-and-route, clock tree synthesis, and timing closure.
- Proficiency with industry-standard EDA tools such as Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, and StarRC.
- Experience with STA and SDC development, low-power design, power and reliability analysis, physical verification, and tapeout on advanced FinFET process nodes.
Nice to have
- Experience implementing memory controllers, NoC, or high-speed interconnect IP and full-chip SoC integration.
- Experience in AI/ML workloads.
Pay
$138,000 — $206,000 USD base salary
Tools
Synopsys Fusion Compiler/ICC2, Cadence Innovus, PrimeTime, StarRC, Tcl, Python, Perl, UPF/CPF
AI focus
Physical design for memory-centric computing IP and SoC partitions serving AI/ML workloads; develop implementation flows using agentic AI tools and frameworks.
Model-written summary · the original posting is authoritative