Samsung
Senior RTL Engineer, IO Die and Interconnect IP
$138K–$206K
San Jose, California, United States · Senior · Full-time · Posted Aug 21, 2026
- Experience
- Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience; separately, 5+ years of RTL development experience is requested.
- Education
- Bachelor’s, Master’s, or PhD.
About the job
Develop and integrate RTL and interconnect IP for Samsung’s IO die and chiplet-based architecture, including UCIe, PCIe, and CXL subsystems.
What you'll do
- Develop IO-die RTL and own microarchitecture for interconnect subsystems and fabric bridges.
- Integrate, configure, and customize interconnect IP; ensure chiplet interface compliance and interoperability.
- Collaborate across verification, architecture, PHY/SerDes, physical design, and software, and automate RTL integration flows.
What they ask for
- 5+ years of RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems.
- Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces.
- Experience modifying or customizing third-party interconnect IP to meet die-level requirements.
- Experience with SoC integration methodologies and scripting (Tcl, Python, or Perl) for design integration and automation.
Nice to have
- Familiarity with agentic AI tools and frameworks.
- Experience in AI/ML workloads.
Pay
$138,000 — $206,000 USD (base salary)
Tools
Verilog, SystemVerilog, UCIe, PCIe, CXL, Tcl, Python, Perl
AI focus
Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks; experience in AI/ML workloads is requested.
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