SiTime
Principal Analog Design Engineer
$119K–$163K
Arizona, Tempe +2 · Principal · Full-time · Posted Oct 16, 2026
- Location
- Arizona, Tempe
United States
United States - Experience
- 10+ years of relevant experience in analog/mixed-signal CMOS design.
- Education
- Master’s or PhD degree in Electrical Engineering.
About the job
Provides technical leadership and hands-on analog circuit design for advanced clock and timing products, guiding development from concept through production release.
What you'll do
- Define, design, and develop circuits for high-performance timing products; support prototype testing, debugging, and lab characterization.
- Mentor junior designers and collaborate with remote engineering and cross-functional teams.
- Provide technical support throughout product development through production release.
What they ask for
- Master’s or PhD degree in Electrical Engineering.
- 10+ years of relevant experience in analog/mixed-signal CMOS design.
- Experience designing PLLs or related circuit building blocks; proficiency with the Cadence analog/mixed-signal simulation toolset.
- Hands-on lab testing and characterization experience; English proficiency for professional communication and collaboration.
Nice to have
- Experience with analog behavioral modeling using SystemVerilog, Verilog-A, or AMS.
- Familiarity with analog/mixed-signal design flow, simulation methods, design rules, and post-layout verification.
Pay
$118,620 — $163,110 USD (base salary)
Tools
CMOS, PLLs, Cadence, SystemVerilog, Verilog-A, AMS, VCXOs, LC-Voltage Controlled Oscillators (VCOs)
Model-written summary · the original posting is authoritative