SiTime
Principal Engineer, Layout Design
California, Santa Clara · Principal · Full-time · Posted Oct 15, 2026
- Experience
- 15+ years.
- Education
- BA/BS degree in Layout Design or a related field, or equivalent experience.
About the job
Leads and performs custom analog layout design for CMOS and BiCMOS circuits, including chip-level integration, verification, and tape-out.
What you'll do
- Design and verify chip-, block-, and cell-level layouts, floor plans, power distribution, shielding, and routing.
- Coordinate and review layout work across design centers; train and mentor junior engineers and offshore contractors.
- Support tape-out and improve shared layout workflows, practices, and quality processes.
What they ask for
- 15+ years of experience in analog and full-custom digital layout design.
- Experience with TSMC 180nm, 65nm, and 22nm process technologies.
- Proficiency with Cadence Virtuoso and working knowledge of DRC, LVS, and ERC debugging using Cadence PVS or Mentor Calibre.
- Experience with chip-level floorplanning, analog block integration, and chip-level integration, verification, and tape-out.
Nice to have
Tools
CMOS, BiCMOS, TSMC 180nm, 65nm, 22nm, Cadence Virtuoso, Cadence PVS, Mentor Calibre
Model-written summary · the original posting is authoritative