SiTime
Principal Engineer, Package Design
$165K–$227K
California, Santa Clara +2 · Principal · Full-time · Posted Oct 15, 2026
- Location
- California, Santa Clara
United States
United States - Experience
- 10+ years’ experience in semiconductor IC packaging technology and methodology.
- Education
- M.S. or PhD. in Mechanical Engineering, Material Science, or another relevant field.
About the job
Leads the design, development, qualification, and production release of custom semiconductor packaging for SiTime’s MEMS-based timing products.
What you'll do
- Develop packaging technologies and lead package design, development, and release-to-production.
- Manage and analyze design-of-experiments and oversee development activities with overseas OSATs.
- Prototype and test custom packages, ensure performance, reliability, and quality, and lead troubleshooting.
What they ask for
- M.S. or PhD. in Mechanical Engineering, Material Science, or another relevant field.
- 10+ years’ experience in semiconductor IC packaging technology and methodology.
- Experience managing overseas OSATs to bring products into production.
- Knowledge of leadframe-based, flip-chip, and substrate-based packages; flip-chip and bumping technologies; and thermal, stress, and electrical package-design considerations.
Nice to have
- Hands-on CAD software experience (AutoCAD preferred but not required).
- Understanding of semiconductor-package thermal, mechanical, and electrical modeling and material characterization techniques such as DMA, TMA, and TGA.
Pay
$164,800 USD–$226,600 USD base salary
Tools
QFN, WLCSP, AutoCAD, DMA, TMA, TGA
Model-written summary · the original posting is authoritative