SiTime
Principal Foundry Interface Engineer
$148K–$204K
California, Santa Clara · Principal · Full-time · Posted Oct 15, 2026
- Experience
- 13+ years with a Master’s degree, or 10+ years of industry experience with a PhD.
- Education
- Master’s degree or PhD in a relevant engineering or physical-science field, including Semiconductor Process Integration, Device Engineering, or Wafer Yield Engineering.
About the job
Leads foundry yield and process improvement, supports fab transfers and development, and serves as the technical liaison between foundries and internal teams.
What you'll do
- Lead yield improvement, manage yield excursions and continuous improvement plans, and oversee safe launch.
- Guide fab transfers and development activities, including wafer lots, process-skew splits, and DOE strategies.
- Analyze device performance and yield metrics, communicate process health, and resolve technical escalations with foundries.
What they ask for
- Master’s degree with 13+ years of experience or a PhD with 10+ years of industry experience in a relevant engineering or physical-science field.
- Proven experience in yield pareto construction, modeling, projection, and long-term yield roadmaps; extensive foundry collaboration and fab-porting experience.
- Experience using PDF Exensio or other Big Data Analysis tools, and expertise interpreting inline, e-test, and SORT product data.
- Deep knowledge of wafer inline inspection methods, SORT programs, and semiconductor device reliability; well versed with DFM techniques and PFMEA.
Nice to have
- AI/ML predictive modeling experience for yield and performance projections; RF semiconductor device modeling experience.
- Mandarin communication ability.
Pay
$148,320–$203,940 USD (base salary)
Tools
PDF Exensio, Big Data Analysis tools, AI/ML
AI focus
AI/ML predictive modeling to improve projection accuracy for test chips and high-volume products, including correlation of inline process metrics with end-of-line yield and performance, is a plus.
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