SiTime
Principal FPGA Design Engineer
$148K–$204K
California, Santa Clara · Principal · Full-time · Posted Oct 15, 2026
- Experience
- 10+ years of hands-on FPGA architecture and development.
- Education
- MS in Electrical Engineering, Computer Engineering, or related field.
About the job
Leads architecture and development of FPGA platforms for testing, characterizing, and validating SiTime’s MEMS timing products.
What you'll do
- Architect and implement FPGA test platforms, owning the lifecycle from RTL design and simulation through timing closure and bring-up.
- Lead cross-functional initiatives, define system requirements, and coordinate integration across hardware, software, test, validation, and production teams.
- Develop reusable FPGA infrastructure, guide design reviews, and mentor engineers.
What they ask for
- MS in Electrical Engineering, Computer Engineering, or a related field.
- 10+ years of hands-on FPGA architecture and development experience.
- Expertise in Verilog/VHDL, simulation tools, and Python or TCL scripting.
- Experience with low-jitter, low-phase-noise, high-fidelity systems; timing analysis, clock-domain crossing, and high-speed interfaces.
Nice to have
- Experience in MEMS or timing product domains.
- Familiarity with hardware/software co-design, embedded systems, production test environments, or ATE systems.
Pay
$148,320.00 – $203,940.00 USD base salary
Tools
Xilinx, Intel/Altera, Verilog, VHDL, ModelSim, Vivado, Python, TCL
Model-written summary · the original posting is authoritative