SiTime
Sr. Engineer, Package Design
$139K–$191K
California, Santa Clara +1 · Senior · Full-time · Posted Oct 15, 2026
- Location
- California, Santa Clara
United States - Experience
- 5+ years’ experience in semiconductor IC packaging technology and methodology.
- Education
- M.S. or PhD in Mechanical Engineering, Material Science, or another relevant field.
About the job
Develops and qualifies custom semiconductor packaging technologies for SiTime’s MEMS-based timing products, from design through production release.
What you'll do
- Develop and lead package design, development, and release-to-production activities.
- Manage and analyze design of experiments and development activities with overseas OSATs; prototype and test custom package designs.
- Ensure package performance, reliability, and quality, and lead troubleshooting of design or performance issues.
What they ask for
- M.S. or PhD in Mechanical Engineering, Material Science, or another relevant field.
- 5+ years’ experience in semiconductor IC packaging technology and methodology.
- Experience managing overseas OSATs to bring products into production.
- Knowledge of leadframe-based, flip-chip, and substrate-based packages; flip-chip and bumping technologies; thermal, stress, and electrical package-design considerations; and hands-on CAD software experience.
Nice to have
- AutoCAD.
- Thermal, mechanical, and electrical modeling for semiconductor packages; material characterization techniques such as DMA, TMA, and TGA.
Pay
$138,800 — $190,850 USD (base salary)
Tools
QFN, WLCSP, AutoCAD, DMA, TMA, TGA
Model-written summary · the original posting is authoritative