ASIC Design Intern

What you'll do

• Develop RTL in Verilog/SystemVerilog for IP based on existing modules or new specifications.
• Document and communicate with Design Verification, Silicon Validation, and Firmware teams to support design quality.

What they ask for

• Currently enrolled in a BS, MS, or PhD program in Electrical Engineering, Computer Engineering, or a related field.
• Proficient in logic design, micro-architecture, and RTL coding in Verilog and/or SystemVerilog.

Nice to have

• Experience or coursework in digital logic design, verification methodologies, and AMBA, PCIe, NAND, or DDR protocols.
• Scripting with Python, Perl, or TCL; Linux command-line experience; proficiency with AI tools for generating synthesizable and functional RTL.

Pay

$35/hr - $45/hr (USD, hourly pay)

Tools

Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl

AI focus

Preferred proficiency in AI tools to generate synthesizable and functional RTL code.