SK hynix
Director of 3D Stacked Logic Design
$250K–$300K
San Jose, CA +1 · Director · Full-time · Posted Sep 3, 2026
- Location
- San Jose, CA
San Jose, California, United States - Experience
- 8+ years of relevant experience.
- Education
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- Visa sponsorship
- Requires newly hired individuals to complete Form I-9 to verify identity and legal authorization to work in the United States; participates in the federal E-Verify program.
About the job
Leads development and customer co-design of high-speed digital IP for 3D-stacked DRAM logic dies, including implementation, verification, and integration into customer systems.
What you'll do
- Lead high-speed digital IP design and implementation for 3D-stacked DRAM peripheral circuits and DFT with U.S.-based customers.
- Drive foundry verification of service-ready IPs and establish infrastructure for the IP business.
- Provide services and co-design support to integrate IP into customer design environments and enable DRAM-on-Logic configurations.
What they ask for
- Bachelor’s degree or higher in Electrical Engineering or a related discipline.
- Development of digital logic IP/SoC using Hardware Description Languages (Verilog, VHDL).
- Experience in RTL design and implementation for memory PHY, high-speed circuit hard macro IP, or high-speed digital IP; memory controller experience; and memory BIST, DRAM DFT, or DFD experience.
- Deep understanding of PPA analysis and optimization, and physical design; excellent English communication and presentation skills.
Pay
$250,000 — $300,000 USD (base salary)
Tools
Verilog, VHDL
Model-written summary · the original posting is authoritative