SK hynix
Director of Buffer & Memory Subsystem Architecture
$250K–$300K
San Jose, CA +1 · Director · Full-time · Posted Sep 1, 2026
- Location
- San Jose, CA
San Jose, California, United States - Experience
- 8+ years
- Visa sponsorship
- New hires must complete Form I-9 to verify identity and legal authorization to work in the United States; the company participates in E-Verify.
About the job
Leads architecture and HW/SW co-design of HBF–xPU systems, translating AI workload traces into memory policies and optimizing system performance.
What you'll do
- Own HBF R&D architecture decisions and coordinate technical alignment with headquarters and external partners.
- Define hardware/software architecture, functional partitioning, and interface contracts across the HBF stack.
- Develop system models and simulators, analyze workloads, and optimize latency, bandwidth, and memory efficiency.
What they ask for
- 8+ years of experience in the listed memory, controller, accelerator, and data-movement architecture areas, including queueing, scheduling, and buffer-management algorithms.
- Expertise in system performance analysis and translating workload traces into architectural policies.
- Proven HW/SW co-design experience translating AI workload, compiler, runtime, and inference-engine behavior into memory-system requirements.
- Experience owning system architecture decisions and developing or extending architectural simulation tools using Python, C/C++, SystemC, or comparable environments.
Pay
$250,000 — $300,000 USD (base salary)
Tools
Python, C/C++, SystemC
AI focus
Architects HBF–xPU memory systems for AI workloads, using workload traces and performance analysis to guide caching, prefetching, scheduling, and data movement.
Model-written summary · the original posting is authoritative