SK hynix
Physical Design Engineer
$160K–$220K
San Jose · Full-time · Posted Oct 7, 2026
- Experience
- 6+ years of hands-on ASIC physical design experience.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Master's preferred.
About the job
Leads physical implementation of high-performance SoC designs from RTL through GDS, optimizing PPA and achieving signoff and tapeout.
What you'll do
- Lead synthesis, placement, clock tree synthesis, routing, timing closure, and signoff for advanced-node designs.
- Own extraction, physical verification, and power-integrity analysis; resolve violations and optimize power grids.
- Develop design flows and automation, mentor engineers, and collaborate across teams to meet tapeout schedules.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 6+ years of hands-on ASIC physical design experience with proven tapeout success.
- Expertise in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools.
- Deep STA and PrimeTime signoff knowledge, plus Calibre physical verification and RedHawk IR drop/EM analysis experience.
Nice to have
- Experience with 5nm or 3nm FinFET designs; low-power design techniques; or ECO and clock reconstruction methodologies.
- Experience leading or mentoring engineers, or exposure to memory-centric systems, chiplets, or D2D interconnects.
Pay
$160,000/yr - $220,000/yr USD base salary
Tools
Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime (PT), StarRC, Quantus, Mentor/Siemens Calibre, Ansys RedHawk(Redhawk-SC), Tcl, Perl, Python
Model-written summary · the original posting is authoritative