Research Scientist - Loop Engineering and AI Infrastructure

What you'll do

• Establish and document best practices for SoC design automation, optimization, and design-space exploration; build reusable co-design loops.
• Measure and compare design correctness, power, speed, area, workload performance, and search cost, documenting results and failures.
• Study AI systems from storage and memory devices through host software, measuring device effects and system bottlenecks and evaluating compute-memory architectures.

What they ask for

• Bachelor’s, master’s, or Ph.D. in electrical engineering, computer engineering, or computer science; a bachelor’s degree should include research depth in computer architecture, computer systems, VLSI, or electronic design automation.
• A record of taking a research question to a measured, written result.
• Strong in Python.
• For loop engineering: experience automating an SoC, RTL, or physical-design flow, including design-space exploration or closed-loop optimization; for AI infrastructure: research on storage or memory devices through a host running an AI workload and their effects on AI performance.

Nice to have

• Hands-on experience with an AI-assisted co-design loop framework such as CHIA or SKHY, or another agentic or scripted flow.
• Proficiency with Chisel, XLS, or RISC-V SoC integration, and RTL simulation or FPGA prototyping.

Pay

$000,000/yr - $000,000/yr (USD, base salary)

Tools

Python, CHIA, SKHY, Chisel, XLS, RISC-V, RTL, FPGA

AI focus

AI-assisted hardware/software co-design loops; research on memory-device effects, system bottlenecks, and compute-memory architectures for AI training and inference.