SK hynix
Sr. Staff / Principal Physical Design Engineer
$160K–$220K
San Jose · Senior Staff · Full-time · Posted Sep 25, 2026
- Experience
- 6+ years of hands-on ASIC physical design experience.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; Master's preferred.
About the job
Leads physical implementation of high-performance SoC designs from synthesis through GDS, optimizing PPA and ensuring signoff and tapeout readiness.
What you'll do
- Lead implementation through synthesis, placement, CTS, routing, timing closure, and signoff for advanced-node blocks or full-chip SoCs.
- Perform timing, extraction, physical verification, and power-integrity analyses; resolve violations and optimize power grids.
- Develop physical design flows and automation scripts, mentor junior engineers, and collaborate across teams to meet tapeout schedules.
What they ask for
- Expert proficiency in synthesis, placement, CTS, and routing using Synopsys or Cadence P&R tools.
- Deep knowledge of STA and PrimeTime signoff, including multi-corner/multi-mode closure.
- Demonstrated Calibre physical verification and RedHawk IR-drop/EM analysis experience.
- Hands-on ASIC physical design experience with proven tapeout success.
Nice to have
- Experience with 5nm or 3nm FinFET process nodes; familiarity with low-power techniques, ECO implementation, or clock reconstruction.
- Experience leading or mentoring engineers; exposure to memory-centric systems or chiplet/D2D interconnects.
Pay
$160,000/yr - $220,000/yr USD base salary
Tools
Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime (PT), StarRC, Quantus, Mentor/Siemens Calibre, Ansys RedHawk(Redhawk-SC), Tcl, Perl, Python
Model-written summary · the original posting is authoritative