SK hynix
Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
San Jose · Senior Staff · Full-time · Posted Apr 13, 2026
- Experience
- 3 - 7 years of experience in ASIC design.
- Education
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About the job
Design and verify high-speed interface IP for next-generation NVMe or chiplet storage subsystems, supporting the design process through silicon bring-up.
What you'll do
- Design and verify high-speed interfaces for next-generation storage subsystems.
- Coordinate efforts with cross-functional teams from RTL development through silicon bring-up.
What they ask for
- Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
- Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
- Experience with Clock Domain Crossing (CDC), timing closure, synthesis flows or Gate Level Simulation (GLS).
Nice to have
- Experience in PCIe (Gen4/5/6) architecture, including TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
- Experience with link training, power states, error handling (AER), cross-functional leadership, or AI Assist design flow.
Tools
Verdi, VCS, Python, Perl, SystemVerilog, Verilog, PCIe
AI focus
AI-assisted design flows are mentioned as a methodology improvement and preferred experience.
Model-written summary · the original posting is authoritative