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Integrated Circuit Design Verification Engineer
$147K–$259K
Vancouver, WA - 805 Broadway · Full-time · Posted Oct 20, 2026
- Experience
- 10+ years of experience in ASIC Design Verification; relevant years of experience may substitute for the stated degree.
- Education
- BSEE or MSEE or relevant years of experience
About the job
Verifies display integrated circuits for augmented reality products as part of a multidisciplinary design team.
What you'll do
- Develop and implement UVM- and assertion-based testbenches; create and execute verification plans with functional and code coverage.
- Use Siemens Questa for verification and debugging, and configure tools and automation.
- Collaborate with digital design, analog logic, software, and verification engineers.
What they ask for
- Strong knowledge of UVM and SystemVerilog.
- Strong knowledge of digital functional simulation and tools such as Siemens Questa.
- Strong knowledge of good Verilog RTL coding practices.
- Scripting and automation skills, such as TCL, Make, Perl, Python, and Shell scripts in a Linux environment; excellent written and verbal English communication.
Nice to have
- Experience with the entire verification process from planning to sign-off, Siemens’ UVM Framework, emulation, or RTL design.
- Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols, embedded microcontrollers, or ASIC test or production flow.
Pay
$173,000-$259,000 annually USD (base salary); $164,000-$246,000 annually USD (base salary); $147,000-$220,000 annually USD (base salary)
Tools
UVM, SystemVerilog, Siemens Questa, Verilog RTL, TCL, Make, Perl, Python
Model-written summary · the original posting is authoritative