SpaceX
Spring 2027 Silicon Engineering Internship/Co-op
Flexible - Any SpaceX Site +9 · Internship · Posted Aug 3, 2026
- Location
- Flexible - Any SpaceX Site
Bastrop, TX, United States
Cape Canaveral, FL, United States
Hawthorne, CA, United States
Irvine, California, United States
McGregor, TX, United States
Memphis, TN
Palo Alto, California, United States
Redmond, WA, United States
Brownsville, TX, United States - Experience
- 3+ months of relevant experience required; 6+ months of relevant internship or project work preferred.
- Education
- Must be enrolled in a bachelor’s degree or graduate program.
- Visa sponsorship
- Applicant must be a U.S. citizen or national, U.S. lawful permanent resident, refugee, or asylee, or be eligible to obtain required authorizations from the U.S. Department of State.
About the job
Work with cross-disciplinary teams on custom in-house silicon and hardware development for deployment on-orbit and in space.
What you'll do
- Contribute to silicon hardware engineering work with a mentor and cross-disciplinary teams.
- Apply engineering knowledge to chip design and development.
What they ask for
- Must be enrolled in a bachelor’s degree or graduate program.
- 3+ months of software development, hardware engineering, or chip design/development experience.
- Able to work full time onsite for at least 12 consecutive weeks beginning in January or March 2027.
- Must meet the stated U.S. citizenship, permanent-resident, refugee, or asylee eligibility criteria, or be eligible to obtain required U.S. Department of State authorizations.
Nice to have
- GPA of 3.5 or above; 6+ months of internship or project work in computer architecture, VLSI design, logic design, or circuit design.
- Understanding of formal methods or verification; experience with C/C++, Verilog, VHDL, Python, Perl, Spice, Timing, Synthesis, Ansys, or COMSOL.
Pay
$30.00/hour USD base salary; $34.00/hour USD base salary; $36.00/hour USD base salary; $38.00/hour USD base salary; $40.00/hour USD base salary
Tools
C/C++, Verilog, VHDL, Python, Perl, Spice, Timing, Synthesis
Model-written summary · the original posting is authoritative