Substrate
Standard Cell Design Lead
$150K–$275K
San Francisco · On-site · Full-time · Posted Oct 28, 2025
- Experience
- 10+ years in standard cell design, library development, and characterization.
- Visa sponsorship
- Applicants must be legally authorized to work in the United States. This position is not eligible for visa sponsorship.
About the job
Develop and optimize standard cell libraries, lead cell characterization and validation, and support integration with digital design flows and fabrication teams.
What you'll do
- Lead library development and optimize cell layouts for power, performance, and area.
- Characterize libraries and develop Liberty timing files and LEF physical abstractions.
- Lead library validation and qualification, including DFM, DRC/LVS, and DFT support.
What they ask for
- Deep understanding of standard cell architecture, layout, and optimization.
- Strong background in cell characterization and Liberty timing model generation.
- Experience with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar.
- Proficiency with characterization tools and SPICE simulation for timing and power analysis.
Nice to have
- Experience with advanced-node standard cells or FinFET/GAA library development.
- Advanced degree in Electrical Engineering or a related field.
Pay
$150,000-$275,000 USD (base salary)
Tools
Cadence Virtuoso, Synopsys Custom Compiler, SPICE, Liberty (.lib), LEF, EDA, DRC/LVS
Model-written summary · the original posting is authoritative