Tensordyne
Mid Level ASIC Design Engineer
Sunnyvale, CA +1 · Full-time · Posted Aug 5, 2026
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 3+ years of ASIC design experience.
- Education
- B.S. in Electrical or Computer Engineering; M.S. preferred.
About the job
Design and implement high-performance AI ASICs, including microarchitecture, RTL, IP integration, synthesis, and support for timing closure.
What you'll do
- Define and document microarchitecture, coordinating changes with architecture.
- Select and integrate third-party IP, and collaborate with design verification engineers.
- Run and analyze frontend synthesis, resolve issues, and guide backend teams on place-and-route and timing closure.
What they ask for
- 3+ years of ASIC design experience, with a track record in RTL logic design for multi-million-gate ASICs using Verilog or System Verilog.
- Experience integrating IP, specifically CPU IP into SoC.
- Knowledge of processor architectures, memory hierarchy, cache coherency, virtual memory, and multicore CPU operation; familiarity with AMBA/APB/AXI and processor peripheral interfaces.
- Hands-on experience across the ASIC development process, proficiency with frontend tools and methodologies, and familiarity with low-power design and UPF.
Nice to have
- Previous experience with timing closure at high frequencies.
- Interest in AI architectures for convolution, transformer, and other workloads.
Tools
Verilog, System Verilog, ARM, RISC-V, MIPS, AMBA, APB, AXI
AI focus
Design high-performance AI ASICs for inference; explore architectures for convolution, transformer, and other workloads. Use GenAI across workflows while retaining ownership and quality of generated collateral.
Model-written summary · the original posting is authoritative