Tensordyne
Senior ASIC Physical Design Engineer
Sunnyvale, CA +1 · Senior · Full-time · Posted Apr 14, 2022
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 5+ years of hands-on ASIC engineering experience.
- Education
- Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field
About the job
Leads hands-on front-end ASIC physical design and workflow development for multimodal generative AI inference acceleration products, improving block- and full-chip implementation and optimization.
What you'll do
- Lead and improve front-end physical design workflows, including synthesis, formal checks, power analysis, and STA guidance.
- Guide colleagues and support backend design across clock trees, routing, DRC, LVS, metal fill, and artwork release.
- Collaborate with ASIC design and verification teams to understand and improve workflows and EDA needs.
What they ask for
- 5+ years of hands-on ASIC engineering experience with deep knowledge of VLSI/SoC physical design workflows.
- Experience with EDA tools such as Cadence/Synopsys (Genus/DC), power analysis, and clock methodology.
- Understanding of STA analysis and constraints at block level and full-chip timing analysis.
- Strong analytical, written, verbal, and collaboration skills.
Tools
Cadence/Synopsys, Genus/DC, STA, DRC, LVS
AI focus
Designs and improves ASIC physical design workflows for multimodal generative AI inference acceleration products.
Model-written summary · the original posting is authoritative