Tensordyne
Sr. ASIC Verification Engineer
Sunnyvale, CA +1 · Senior · Full-time · Posted Jun 17, 2026
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 4-8 years of ASIC verification experience, including taking multiple chips through the full verification and post-silicon validation cycle.
- Education
- B.S. in Electrical or Computer Engineering or a similar field; M.S. preferred.
About the job
Leads end-to-end ASIC verification, from architecture and planning through tapeout and post-silicon validation, for processors accelerating generative AI inference.
What you'll do
- Develop and lead block, subsystem, and full-chip verification plans, environments, tests, and reusable methodologies.
- Drive verification signoff, bug triage, coverage convergence, and regression debugging in collaboration with design and architecture teams.
- Mentor verification engineers and perform diagnostic and post-silicon validation tests in the lab.
What they ask for
- Expertise in SystemVerilog, UVM, constraint randomization, and functional coverage.
- Experience with C/C++ or System-C and object-oriented programming, constrained-random stimulus, and coverage-driven verification.
- Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM, or SerDes.
- B.S. in Electrical or Computer Engineering or a similar field.
Nice to have
- M.S. degree.
- Scripting experience with Python, Perl, TCL, or shell programming.
Tools
SystemVerilog, UVM, C/C++, System-C, PCIe, Ethernet, DDR/HBM, SerDes
AI focus
Verifies processors for generative AI inference acceleration; the posting also expresses interest in AI architectures for convolution, transformer, and other workloads.
Model-written summary · the original posting is authoritative