Tensordyne
Sr. Staff ASIC Design Engineer
Sunnyvale, CA +1 · Senior Staff · Full-time · Posted Aug 4, 2022
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 10+ years of ASIC design experience.
- Education
- B.S. in Electrical or Computer engineering; M.S. preferred.
About the job
Design and implement microarchitecture and RTL for high-performance, low-power AI inference ASICs, including CPU and other IP integration and silicon validation.
What you'll do
- Write microarchitecture specifications, review specifications and test plans, and architect and implement complex RTL designs.
- Integrate CPU and other IP, and collaborate with physical design to address timing and power optimization.
- Analyze coverage, support verification closure, perform post-silicon diagnostics, and assist with lab software bring-up.
What they ask for
- 10+ years of ASIC design experience, including RTL design for multi-million-gate ASICs using Verilog or System Verilog.
- Experience integrating IP, specifically CPU IP into SoC.
- Knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, cache coherency, virtual memory, multicore CPU operation, and AMBA/APB/AXI Protocol.
- Hands-on ASIC development experience and familiarity with processor peripheral interfaces and low-power design, including UPF flow.
Nice to have
- Previous experience with timing closure at high frequencies.
- Interest in AI architectures for convolution, transformer, and other workloads.
Tools
Verilog, System Verilog, ARM, RISC-V, MIPS, AMBA/APB/AXI Protocol, UPF, SPI
AI focus
Design high-performance, low-power AI ASICs for inference, with interest in architectures for convolution, transformer, and other workloads.
Model-written summary · the original posting is authoritative