Tensordyne
Sr. Staff ASIC Verification Engineer
Sunnyvale, CA +1 · Senior Staff · Full-time · Posted Jun 4, 2026
- Location
- Sunnyvale, CA
San Jose, California, United States - Experience
- 15+ years of ASIC verification experience.
- Education
- B.S. in Electrical or Computer Engineering (or similar field); M.S. preferred.
About the job
Lead ASIC verification from architecture through tapeout and post-silicon validation for processors that accelerate generative AI inference.
What you'll do
- Plan and lead block-, subsystem-, and full-chip verification, including test strategies, environments, tests, and reusable methodologies.
- Drive verification signoff by debugging issues, managing bugs and regressions, and converging coverage and quality metrics.
- Mentor verification engineers and perform diagnostic and post-silicon validation in the lab.
What they ask for
- 15+ years of ASIC verification experience, including taking multiple chips through verification and post-silicon validation.
- Expertise in SystemVerilog, UVM, constraint randomization, and functional coverage.
- Experience in C/C++ or System-C; deep understanding of object-oriented programming, constrained-random stimulus, and coverage-driven verification.
- Verification experience with high-speed interfaces such as PCIe, Ethernet, DDR/HBM, or SerDes.
Nice to have
- Scripting experience in Python, Perl, TCL, or shell programming.
- M.S. degree in Electrical or Computer Engineering (or similar field).
Tools
SystemVerilog, UVM, C/C++, System-C, Python, Perl, TCL, PCIe
AI focus
Verifies processors designed for generative AI inference acceleration; the posting also notes interest in AI architectures for convolution, transformer, and other workloads.
Model-written summary · the original posting is authoritative